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Sandy Bridge is the codename for a microarchitecture developed by Intel beginning in 2005 for central processing units in computers to replace the Nehalem microarchitecture. Intel demonstrated a Sandy Bridge processor in 2009, and released first products based on the architecture in January 2011 under the Core brand.〔 Developed primarily by the Israeli branch of Intel, the codename was originally "Gesher" (meaning "bridge" in Hebrew).〔(【引用サイトリンク】title=Origin of a Codename: Ivy Bridge )〕 Sandy Bridge implementations targeted a 32 nanometer manufacturing process, while Intel's subsequent product, codenamed ''Ivy Bridge'', uses a 22 nanometer process. The Ivy Bridge die shrink, known in the Intel Tick-Tock model as the "tick", is based on FinFET (non-planar, "3D") tri-gate transistors. Intel demonstrated the Ivy Bridge processors in 2011. ==Technology== Developed primarily by the Israel branch of Intel, the codename was originally "Gesher" (meaning "bridge" in Hebrew). The name was changed to avoid being associated with the defunct Gesher political party; the decision was led by Ron Friedman, vice president of Intel managing the group at the time. Intel demonstrated a Sandy Bridge processor with A1 stepping at 2 GHz during the Intel Developer Forum in September 2009. Upgraded features from Nehalem include: * Intel Turbo Boost 2.0.〔http://www.hotchips.org/wp-content/uploads/hc_archives/hc23/HC23.19.9-Desktop-CPUs/HC23.19.921.SandyBridge_Power_10-Rotem-Intel.pdf〕〔http://www.tomshardware.com/reviews/sandy-bridge-core-i7-2600k-core-i5-2500k,2833-3.html〕〔http://www.intel.com/content/www/us/en/architecture-and-technology/turbo-boost/turbo-boost-technology.html〕 * 32 KB data + 32 KB instruction L1 cache (4 clocks) and 256 KB L2 cache (11 clocks) per core. * Shared L3 cache includes the processor graphics (LGA 1155). * 64-byte cache line size. * Two load/store operations per CPU cycle for each memory channel. * Decoded micro-operation cache (uop cache) and enlarged, optimized branch predictor. * Improved performance for transcendental mathematics, AES encryption (AES instruction set), and SHA-1 hashing. * 256-bit/cycle ring bus interconnect between cores, graphics, cache and System Agent Domain. * Advanced Vector Extensions (AVX) 256-bit instruction set with wider vectors, new extensible syntax and rich functionality. * Intel Quick Sync Video, hardware support for video encoding and decoding. * Up to 8 physical cores or 16 logical cores through Hyper-threading. * Integration of the GMCH (integrated graphics and memory controller) and processor into a single die inside the processor package. In contrast, Sandy Bridge's predecessor, Clarkdale, has two separate dies (one for GMCH, one for processor) within the processor package. This tighter integration reduces memory latency even more. * A 14- to 19-stage instruction pipeline, depending on the micro-operation cache hit or miss. : : All translation lookaside buffers (TLBs) are 4-way associative.〔Result of running cpuid〕 抄文引用元・出典: フリー百科事典『 ウィキペディア（Wikipedia）』 ■ウィキペディアで「Sandy Bridge」の詳細全文を読む スポンサード リンク
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